As the dimensions of integrated circuits continue to decrease, the planarization of a semiconductor architecture continues to be critical to the successful formation of its topographical features, such as trench isolation and one or more layers of interconnects. Typically, the material used to form the interconnects is deposited in a non-selective manner onto the substrate in a blanket deposition and then is selectively etched to form the conductor pattern. Prior to being etched, the material used to form the interconnect is first masked with a photoresist material.
When a photoresist layer is formed on a layer of interconnect material from which an interconnect stud is to be formed, it is essential that the photoresist layer be formed so that the resultant interconnect studs are properly formed and positioned in the desired trenches. Misalignment of the photoresist layer results in studs being partially formed in the desired trench, being malformed and/or being misaligned. When the studs are partially formed in the trench, malformed and/or misaligned, the semiconductor part being formed is rendered useless and must be discarded.
When an interconnect stud is formed between a pair of interconnect lines, a layer of a dielectric material is typically formed over the interconnect lines to insulate the interconnect lines from the stud. The layer of dielectric material is formed, prior to the interconnect stud being formed, in the trench between the word lines to insulate the word lines from the interconnect stud. This layer of dielectric material is commonly referred to as a "spacer." Spacers are typically formed from materials compatible with a silicon process, such as Si0.sub.2 and Si.sub.3 N.sub.4. Once the spacer is formed on the walls of a trench, the width of the trench narrows. The narrowed trench causes the contact area for the subsequently formed interconnect stud to be smaller and causes the subsequently formed interconnect stud to also be narrower than it would be if no spacer were formed in the trench. Narrow interconnect studs make it difficult to form electrical connections with the studs when subsequent layers of the integrated circuit are formed. To combat this problem, prior art interconnect studs are formed so that a portion of the stud extends above the surface of the adjacent interconnect line or other semiconductor structure.
A prior art semiconductor device 150 is shown in FIG. 8. As shown in FIG. 8, a stud 152 is formed in a trench 154 between a pair of interconnect lines 156. The stud 152 has a head 158 and a body 160. A pair of spacers 162 is formed on the sidewalls of the interconnect lines 156. The trench 154 has a width of W.sub.T and each spacer 162 has a width of W.sub.S. As can be seen in FIG. 8, the body 160 of the stud 152 has a width of W.sub.T -2W.sub.S, assuming that each spacer 162 has the same width. In other words, the trench 154 is narrowed by two times the width of the spacer 162 and subsequently so is the width of the body 160 of the stud 152. To compensate for the narrowing of the body 160 of the stud 152, the stud 152 is formed so that its head 158 extends above the surface of the semiconductor device 150 and so that its head 158 has a width which exceeds the dimensions of the trench 154. However, by forming the stud 152 to have a head 158 which exceeds the dimensions of the trench 154 and which extends above the surface of the semiconductor device 150, the likelihood of the stud 152 coming into contact with another area of electrical activity on the semiconductor device 150 is increased. Also, by extending the stud 152 above the surface of the semiconductor device 150, it becomes more difficult to planarize the semiconductor device 150.
Thus, a need has arisen in the art for a method which can be used to form interconnect studs without the use of a masking step. By eliminating the masking step, one can more quickly complete the manufacturing process and ensure proper formation and alignment of the interconnect studs in their desired trenches. A need also exists in the art for semiconductor devices which include studs that are isolated from other areas of electrical activity on the semiconductor device. Finally, a need also exists for a method to form interconnect studs in trenches insulated by a spacer so that the interconnect studs have broad electrical contact surfaces.